A one-bit DAC

To play sound, the computer has to make a voltage that goes smoothly up and down, thousands of times a second. An FPGA pin can only be high or low. The usual answer is a chip that turns numbers into voltages (a DAC, a digital-to-analogue converter), with many pins. This page does without one: a single pin, switching very fast, and a resistor and capacitor on the board to smooth it. It’s the same idea as the DSP site’s one-bit sigma-delta, built in gateware.

1 · Averaging bits

PWM already makes an average: on for part of the time, off for the rest, and anything slow sees the share of time on. To turn that into a voltage, put a resistor in series with the pin and a capacitor to ground after it. The capacitor charges a little while the pin is high and discharges a little while it’s low, so its voltage settles at the average, wobbling slightly about it: a low-pass filter, letting slow changes through and smoothing fast ones away.

The voltage after the carrier board’s RC filter, close up, with the pin at a steady level made three ways (more of them in the next sections). It settles at the same average for all three; the difference is the ripple, the wobble that’s left. Untick the second stage to see one resistor and capacitor alone. PWM’s ripple is the worst by far, more than a volt: its pulses are long, 256 clocks a period, so the capacitor has time to charge and discharge. Untick PWM to see the other two close up: a millivolt or so.

2 · Why PWM is poor for sound

For a light, PWM is perfect. For sound it has two problems:

Its period is slow. 256 clocks of 12 MHz is 46,875 periods a second, so everything it does is in steps of that: a whistle at 47 kHz and its harmonics, only a few times higher than the highest note anyone can hear. The filter has to be very steep to remove it without dulling the sound.
It has only 256 levels: 8 bits, and each sample’s level lasts a whole period. Coarse, and the steps add noise of their own.

Both come from putting all the 1s of a period together. A better scheme would spread them out: the same share of 1s, but scattered evenly, so the average is there almost at once and the ripple is fast and small.

3 · Sigma-delta: a running total of the error

A sigma-delta modulator does exactly that. Every clock it decides 1 or 0, and keeps a running total of how far its output has been from what it was asked for:

add the wanted level to the total;
take away what was put out last time (full scale up for a 1, full scale down for a 0);
put out a 1 if the total is above zero, else a 0.

If it has put out too many 1s lately, the total goes down and it puts out a 0, and the other way round. The error never builds up; on average, the output is the wanted level exactly. “Delta” is the difference, “sigma” the sum of them: the name says what it does.

The same steady level made three ways: 256 clocks of each (a whole period of the PWM), after it has settled. The level runs from −90% of full scale (nearly all 0s) to +90% (nearly all 1s); at 0, half the bits are 1s. All three give the same share of 1s, so the same average: only the pattern differs. PWM puts its 1s together at the start of the period; sigma-delta scatters them as evenly as it can.

If both orders get the average exactly right, what is the second-order modulator for? Not the average, and not the speed: both put out a bit every clock. It’s for the pattern, and so for where the leftover error goes.

The output is always wrong (full scale up or down, never the level asked for), and what makes the error harmless is that it changes quickly: an error that flips back and forth every clock or two is a high frequency, which the RC filter removes. A first-order modulator keeps one running total of the error, and that makes its leftover error mostly fast, but some of it still changes slowly enough to land in the audio band. A second-order modulator keeps a second running total, of the first: it corrects not just the error but the error’s own drift, so even less of it is slow. Its pattern looks busier for exactly that reason. Section 4 shows the difference as a spectrum: the noise left in the audio band is about 40 dB lower.

There’s a price: with two totals the modulator can be pushed too far. Asked for a level right at full scale, its second total grows without end until it overflows, and the bits become nonsense. That’s why the slider stops at ±90%, and why dac.v keeps its mix inside about 60% of full scale. Here’s its modulator, both orders:

reg  signed [19:0] s1, s2;                          // the running totals
wire signed [19:0] n1 = s1 + x_fb;                  // + the wanted level − the last output
wire signed [19:0] n2 = s2 + n1 + (out ? -20'sd32768 : 20'sd32768);
always @(posedge clk) begin
    s1  <= n1;
    s2  <= first ? 20'sd0 : n2;
    out <= first ? n1 >= 0 : n2 >= 0;                // 1 if the total is above zero
end

The input is a 16-bit sample, −32,768 to 32,767, and the output bit stands for +32,768 or −32,768. The site’s TypeScript copy of it (which drew the figures) gives the same bits as the Verilog, checked in Icarus.

4 · Where the noise goes

Every one-bit output is wrong, all the time: it’s always full scale up or down, never the level asked for. That error is noise, and lots of it. The trick of sigma-delta is not to make less of it but to put it somewhere harmless: at high frequencies, far above hearing, where the RC filter removes it. That’s noise shaping.

The spectrum of each method’s bits, playing a sine of about 1 kHz at half full scale, from 200 Hz up to 6 MHz (half of 12 MHz). The shaded band is what we hear, to 20 kHz. PWM’s noise and whistles are spread everywhere, including the audio band. The sigma-delta modulators’ noise is low at the bottom and rises with frequency: steeply for the second order. With the RC filter ticked, its response (dashed) and what’s left after it.

How much noise is left in the audio band decides how good it sounds. For a half-scale tone near 1 kHz, measured on the modulators’ bits (with a perfect filter at 20 kHz): PWM leaves the tone about 35 dB above its noise, the first-order modulator 64 dB, the second-order 104 dB, better than a CD’s 16 bits. One wire, a resistor and a capacitor. (A real board falls short of that: its supply’s noise and the pin’s uneven edges come through too. But it’s far better than PWM.)

5 · Choosing R and C

The filter has to pass 20 kHz and remove what’s above. One resistor and capacitor fall away gently, by 6 dB each time the frequency doubles, so the carrier board uses two stages, falling 12 dB per doubling. The second stage has ten times the impedance of the first (10 kΩ and 470 pF after 1 kΩ and 4.7 nF), so it barely loads the first: two equal stages would drag each other’s corner down, to 12.7 kHz.

	1 kΩ, 4.7 nF, then 10 kΩ, 470 pF
at 20 kHz	−2.9 dB
at 1 MHz	−59 dB
at 6 MHz	−90 dB

The filter’s output can’t drive anything much, so a buffer (an op-amp) follows it, then the volume control and the headphone amplifier. And the pin’s high level is the FPGA’s 3.3 V supply itself: any noise on the supply rides on every 1. Boards that care pass the bit through one more gate, powered from a quiet supply of its own.

6 · Sound from the CPU

The DAC plays what’s mixed into it: the sound chip of the next page, the tone of part 2, and two registers the CPU can write samples to itself.

Address	Register
$8070	LEFT	a sample for the left channel: signed, −128 to 127
$8071	RIGHT	the same, right
$8072	CTRL	bit 0: first-order modulator (else second); bit 1: tone off; bit 2: sound chip off

The computer with the DAC’s sample registers at $8070. Tick sound and run. A tone from samples writes the next of 32 samples of a sine wave 8,000 times a second, from a timer interrupt: a tone of 250 Hz. Two notes adds two sine waves, 250 and 375 Hz (a fifth apart), each with a phase that moves on by its own step each sample. This computer plays the samples; on the board they’d go through the modulator and the RC filter.

Eight thousand samples a second keeps the CPU busy. Measured on this emulator, the one tone’s interrupt handler takes 47% of its time, the two notes’ 82%: a third note wouldn’t fit. That’s what the next page’s sound chip is for: it makes three voices, with envelopes and a filter, on its own, and the CPU only has to say which notes.

Summary

A resistor and capacitor average a fast stream of bits into a voltage, with some ripple left over.
PWM bunches its 1s together: slow ripple, few levels, and whistles near the audio band.
A sigma-delta modulator keeps a running total of its error and scatters its 1s, so its noise is mostly at high frequencies (noise shaping), more so for the second order.
Two RC stages, the second of higher impedance, keep the audio and remove the rest.