Memory and buses

Part 1 built everything a processor computes with: gates, adders, registers, an ALU. But a processor holds only a few numbers at a time, in a handful of registers. Its program, and everything the program works on, lives in memory, separate chips that the processor talks to over a set of shared wires, the bus. This page builds memory from registers, connects it up, and looks at how the 6502 uses it, one clock cycle at a time.

Hex numbers are written with a $, as in 6502 assembly: $FFFF is 65,535.

1 · A memory is many registers

Stack registers in a column and number them: the number is each one’s address. Two circuits from Combining gates make it a memory. To write, a decoder turns the address into “this row”: only that row’s register gets its load signal (as on the register), so only it takes the new data. To read, a multiplexer uses the same address to pass that one row’s contents out.

Pick an address to read it; set data in and click Write to store it.

Eight addresses of 8 bits each. Click the address bits: the decoder lights one row, and the multiplexer passes it out. Set data in and click Write to store it in the addressed row. Every other row keeps its contents.

That’s RAM, random-access memory: “random access” because any address can be read or written as quickly as any other, unlike a tape, which has to wind to the right place first.

2 · Addresses and the memory map

An address of n bits picks one of 2ⁿ locations. The 6502 has 16 address lines, so it can reach 2¹⁶ = 65,536 addresses, $0000 to $FFFF, each holding a byte: 64 KB, its whole world. Everything it talks to has to be in there somewhere, not only memory but input and output too: a keyboard or a display is just a few addresses that behave specially (memory-mapped I/O).

How those addresses are shared out is the system’s memory map. These pages use a simple one:

$0000–$7FFF: RAM, 32 KB. The 6502 needs RAM at the bottom: it keeps fast-access variables in the first 256 bytes (the zero page) and its stack in the next 256.
$8000–$BFFF: I/O, 16 KB of addresses, though a few would do.
$C000–$FFFF: ROM, 16 KB. The 6502 needs ROM at the top: when it starts up, it reads where to begin from $FFFC and $FFFD, so something has to be there before any program has run.

3 · The bus

The processor, the RAM, the ROM and the I/O chips all share the same wires:

the address bus, 16 lines, driven by the processor: where;
the data bus, 8 lines, which carry a byte either way: what;
a read/write line, from the processor: which way.

Sharing raises a problem. On a read, the chip being read has to drive the data bus, and every other chip mustn’t. If two chips drive the same wire and one says 1 while the other says 0, current flows straight from one chip’s supply, along the wire, into the other’s ground: a short circuit, drawn red in these figures. So every chip’s data outputs are tri-state: besides 1 and 0, they can let go of the wire altogether, leaving it floating. Only the selected chip drives; the rest let go.

Deciding which chip is selected is address decoding, and with this memory map it takes just the top two address bits: A15 = 0 means RAM; A15 and A14 = 10 means I/O; 11 means ROM.

Slide the address and watch the memory map’s pointer and which chip is selected: it drives the data bus on a read, or takes the data on a write; the others let go (dashed). Then tick Break the I/O chip’s decoding, which makes the I/O chip forget A14 and answer anywhere from $8000 up. The figure jumps to a read from the ROM’s addresses, where two chips now drive the data bus at once (red). Slide back below $C000 and the fault hides again.

That fault is real, and it has a name: bus contention. It gives garbage data at best, and at worst damages the chips, which is why address decoding is one of the first things checked when a new board misbehaves.

4 · ROM: a stored truth table

ROM, read-only memory, can be read like RAM but not written: its contents are fixed when it’s made, or programmed in specially. A ROM with an n-bit address and m-bit data is a truth table with n inputs and m outputs, stored rather than built from gates. So any truth table can be a ROM.

The 7-segment display’s truth table took 39 gates even simplified. As a ROM it’s 16 bytes: the address is the digit, and each byte says which segments to light, one bit per segment.

A 16-byte ROM holding the 7-segment table, with the hex letters A to F filling the six addresses the display page left as don’t-cares. Click the address bits: the ROM looks up the byte, and its bits light the segments.

The first ROMs were made with their contents built in, as part of the chip’s wiring (mask ROM). EPROMs could be programmed by the user and erased by ultraviolet light through a little quartz window on top. Today it’s flash, which is erased and rewritten electrically, in blocks: the memory in a USB stick, and the chip that holds an FPGA’s configuration.

5 · Real memory cells

A register built from flip-flops, as in section 1, takes a lot of transistors per bit. Real memory chips use much smaller cells, of two kinds:

Static RAM (SRAM) is the ring of two inverters, plus two transistors to connect it for reading and writing: six transistors per bit. It holds its bit as long as it has power, and it’s fast. Processors use it for their registers and caches.
Dynamic RAM (DRAM) stores each bit as a tiny charge on a capacitor, behind one transistor: one transistor and one capacitor per bit, so it packs many times more bits into the same space. But the charge leaks away, so every cell has to be read and written back, refreshed, before it fades too far. The usual standard is every 64 milliseconds.

A byte of DRAM, as charge on eight capacitors, with time slowed down and the leak exaggerated so it can be seen. A cell reads as 1 while its charge is above the dashed line. With refresh on, every 64 ms each cell is read and written back at full charge. Turn refresh off, and within about 100 ms the 1s fade to 0s.

That trade, dense and cheap but needing refresh, against fast but big, is why a computer’s main memory is DRAM, and the small fast memories inside the processor are SRAM.

6 · The 6502’s bus cycle

The 6502 uses the bus in every single clock cycle: each cycle is one read or one write. Its clock comes in two phases, φ1 and φ2. They’re the same square wave, one the opposite of the other, with a small gap at each change so they’re never both high at once; the 6502 makes both from a single clock fed into it. φ1 is high in the first half of each cycle, φ2 in the second.

φ1: just after the cycle starts, the 6502 puts the address out and sets the read/write line.
φ2: the data moves. On a write, the 6502 drives the data bus; on a read, the memory does.
φ2 falling, at the end of the cycle, is the edge that matters: on a read, the 6502 takes the byte from the data bus then; on a write, the memory takes it.

So an instruction is a sequence of memory accesses. LDA $1234 (load A from address $1234) is three bytes long, and takes four cycles: read its opcode, read the two bytes of the address, then read the value from $1234.

LDA $1234 then STA $1235, cycle by cycle: each column is a clock cycle, φ1’s half then φ2’s, and the little markers show φ2 falling, when the data is taken. Step through with the buttons. Every cycle reads, except the last, which writes. Then tick Share the bus with a video chip.

The bus sits idle during φ1, and home computers made good use of it. In the Commodore 64, the video chip reads the screen from memory during φ1, so it can draw the picture without slowing the processor down. (On some lines it needs more than that, and briefly stops the processor to take whole cycles.) The Apple II does the same, and its video reads double as the refresh its DRAM needs.

7 · Why memory is slower than logic

In the 6502’s day, memory kept up with the processor: a cycle at 1 MHz is a microsecond, and memory chips of the time could answer in a fraction of that. Since then, processors have got faster much more quickly than memory has.

A memory is slow for the reasons this page has built up. An address has to go through a big decoder, then drive a long wire across thousands of cells; the selected cell, tiny and weak, has to pull on another long wire, the bit line, shared with thousands more; and a DRAM cell’s tiny charge needs amplifying before it can be read. And main memory is on separate chips, so every access also crosses the circuit board.

A modern processor’s DRAM takes something like 100 nanoseconds to answer, a few hundred cycles of a 4 GHz clock. That gap, the memory wall, is why processors keep copies of recently used memory in small, fast SRAM caches beside them.

Summary

A memory is a column of registers: a decoder picks the row to write, a multiplexer the row to read.
n address bits reach 2ⁿ locations: the 6502’s 16 give 64 KB. The memory map shares them out between RAM, ROM and I/O, which is just addresses that behave specially.
Chips share a bus: address, data and read/write. Outputs are tri-state, so only the selected chip drives the data bus; address decoding picks it. Two at once is bus contention.
A ROM is a stored truth table: the 7-segment decoder is 16 bytes.
SRAM (six transistors a bit) is fast; DRAM (one transistor and a capacitor) is dense but leaks, and is refreshed every 64 ms.
The 6502 accesses the bus every cycle, with two opposite clock phases: address in φ1, data in φ2, taken as φ2 falls. Video chips used the free φ1 halves.
Memory has fallen far behind logic in speed: the memory wall.