I²C
SPI needs four wires, and one more for each extra device. I²C (said “I squared C”, the Inter-IC bus) manages with two, however many chips share them: one for the clock, SCL, and one for the data, SDA, both ways. Temperature and humidity sensors, small memories, clocks that keep time with the power off, little displays, motion sensors: a great many small chips speak it, and the carrier board has a connector for them. The price is speed (100 or 400 kHz, against SPI’s tens of MHz) and a cleverer set of rules.
1 · Open drain: nobody can fight
Section titled “1 · Open drain: nobody can fight”Two wires shared by many chips, each of which sometimes sends: on an ordinary bus, two chips driving the same wire to different levels would short the supply through their outputs (as on Memory and buses). I²C’s answer is that nobody ever drives a wire high. Each chip’s output can only pull the wire low, or let go of it (an open-drain output: a transistor to ground, and nothing to the supply). A resistor pulls the wire up to 3.3 V whenever nobody is pulling it down.
Three parts sharing SDA through open-drain outputs. Each can pull the wire low (a switch to ground) or let go; the pull-up resistor holds it high when nobody’s pulling. Several pulling at once is harmless: the wire is just low, and the only current is through the resistor. So the wire is 1 only if every part lets go: a wired AND.
That makes a fight impossible, and it gives I²C two tricks for free. A device can acknowledge a byte by pulling SDA low while the sender lets go of it. And a slow device can hold SCL low to make the controller wait (clock stretching): the controller lets go of SCL to raise it, and doesn’t carry on until it really is high. The cost is the pull-up: a wire rises only as fast as the resistor can charge it, which is what limits I²C’s speed.
2 · Messages, drawn on the wires
Section titled “2 · Messages, drawn on the wires”SDA only changes while SCL is low; while SCL is high, SDA holds still and is read. So a change of SDA while SCL is high can’t be data, and I²C uses the two such changes as signals:
- START: SDA falls while SCL is high. Every message begins with one.
- STOP: SDA rises while SCL is high. The bus is free again.
Between them, bytes, highest bit first, each followed by a ninth bit, the acknowledgement: the receiver pulls SDA low (ACK) to say it got the byte, or leaves it high (NACK). The first byte after a START is an address: 7 bits saying which chip, and an eighth saying whether the controller wants to write (0) or read (1). Only the chip with that address answers; if nobody has it, nobody acknowledges.
An I²C transaction, as SCL and SDA. Orange is the CPU driving SDA, blue the device. Read the temperature: START, address $48 with write, the register number 0, then a repeated START (a START without a STOP before it, so no other controller can take the bus in between), address $48 with read, and two bytes from the sensor; the CPU acknowledges the first and not the second (NACK: “that’s all I want”), then STOP. Address $52: no device has it, nobody pulls SDA low in the ninth bit, and the CPU sees a NACK.
Reading from most devices works like the first transaction: write to say which of its registers, then read from there. The device remembers where it is and moves on a byte for each byte read.
3 · The I²C port
Section titled “3 · The I²C port”i2c.v works in steps the CPU asks for: a START, a byte out, a byte in, a STOP. Each takes the bus through a
bit’s worth of quarter-steps: set SDA while SCL is low, let SCL go high (and wait, if a device is holding it
low), read SDA in the middle, pull SCL low again. At the speed after reset, a quarter is 31 clocks of 12 MHz:
97 kHz, close to the standard 100. A byte, with its acknowledgement, takes 93 µs.
| Address | Register | |
|---|---|---|
| $8060 | DATA | the byte to send; after a read, the byte received |
| $8061 | CMD (write) | bit 0: START (or a repeated START); bit 2: send DATA; bit 3: receive a byte (bit 4: answer NACK, for the last); bit 1: STOP. Any together, in that order |
| $8061 | STATUS (read) | bit 7: busy; bit 0: the last byte sent wasn’t acknowledged |
| $8062 | SPEED | a quarter of SCL’s period is SPEED + 1 clocks: 30 after reset, for 97 kHz; 7 for 375 kHz, near the fast speed of 400 |
The computer with I²C at $8060, a temperature sensor at $48 and a small memory (an EEPROM) at $50, printing on the serial terminal. Read the temperature reads the sensor twice a second: move its slider. Who’s on the bus? tries every address and prints the ones that answer. Store and read back writes five bytes into the EEPROM, then reads them back. Below the terminal, each step on the bus.
The sensor here behaves like the common ones (a register 0 with the temperature in two bytes: whole degrees, then half a degree in the top bit), and an EEPROM is memory that keeps what’s written with the power off, slow to write and good for settings. On the board, any I²C module with a 3.3 V supply can plug into the carrier’s I²C connector, and the scanning program finds it.
Every device’s address is fixed by its maker (some let you change a bit or two with a pin), and there are only 112 usable ones, so two of the same chip on one bus need different settings of those pins. The scanner is the first thing to run when a new device doesn’t answer: if its address isn’t in the list, check the wiring.
Summary
Section titled “Summary”- I²C shares two wires, SCL and SDA, among many chips, using open-drain outputs and pull-up resistors: anyone can pull a wire low, nobody drives it high, so nobody can fight.
- START and STOP are SDA changing while SCL is high; everything else changes SDA only while SCL is low.
- Each byte is followed by an ACK (pulled low) or NACK; the first byte is a 7-bit address and a read/write bit.
- A slow device can stretch the clock by holding SCL low.
Further reading
Section titled “Further reading”- NXP’s I²C-bus specification and user manual (UM10204): the bus’s own definition, readable and free.